1. Field of the Invention
The present invention relates to the field of reclamation and reuse of semiconductor material substrates. More particularly this invention relates to an apparatus and method for inspecting incoming and outgoing wafers at a reclaim factory.
2. Discussion of Related Art
The increasing process complexity and introduction of new materials to the field of integrated circuit (IC) fabrication has given rise to a greater number of processing steps; each of which must be tested for quality.
Test wafers including “dummy” or “control monitor” wafers are used to check the reliability of IC fabrication equipment. For example, dummy wafers are used to test new IC fabrication equipment prior to its implementation into the large-scale production process of ICs. A dummy wafer is cycled through the new equipment and the ICs formed on the dummy wafer are then examined to determine if they meet certain specified criteria indicating that the fabrication process was properly performed. Only then is the equipment implemented into the production of ICs. Thereafter, the dummy wafer may be discarded, or “recycled” by removing the depositing films and re-using the dummy wafer.
Once fabrication equipment is implemented into the production process, it must be periodically inspected by examining the fabricated ICs to ensure that it is functioning properly. Such quality assurance testing is typically performed on a daily basis, such as at the beginning of every working shift. During such testing, control monitor wafers are used in a trial process, such as film deposition, performed on the wafer. The control wafer is then examined to determine if it meets certain specified criteria indicating that the fabrication process was properly performed. Thereafter, the control wafer maybe discarded (to protect intellectual property, for example), or “recycled” by removing the depositing films and re-using the control wafer.
All of this quality assurance testing requires the use of a large number of wafers and increases the total cost of IC fabrication. Customers will typically recycle their wafers using their own equipment. However, each recycle roughens the wafer surface and after a few such cycles the wafers must be re-polished to meet fab specifications for such wafers to be used in their tools. These wafers are typically sent to a wafer reclaim vendor who provides the essential expertise and service for stripping and re-polishing the wafers to the customer's specifications and returning them to the customer for a service charge. In addition to meeting customer specifications, the wafer reclaim vendor must ensure than one customer's wafers do not become mixed with another customer's wafers. The method typically employed to accomplish this is to record each wafer's identification (ID) code at the incoming stage and then tracking that wafer through the entire process.
The reclamation cycle forms a loop in which used wafers are sent to a reclaim vendor, processed to meet fab specification, and sent back to the customer for reuse as test wafers. Customers optimize cost-cutting by reducing the number of test wafers to be used, and by using them as many times as possible. This requires maintaining a high ratio of reclaimed wafers to total test wafers. In order to meet customer demands, wafer reclaim factories must in turn optimize the wafer reclaim process and offer cycle times in the order of days rather than weeks.
A typical wafer reclamation process includes multiple preliminary steps of incoming wafer inspection, ID detection, and sorting of the wafers into groups. The grouped wafers are then subjected to removal steps such as grinding and/or etching particular materials, followed by polishing and cleaning. The process is finalized with a final multi-step outgoing wafer inspection to ensure that the proper amount of material was removed, and that customer specifications such as those for surface particles and wafer flatness are met. A lot of attention has been given to optimization of the critical removal steps where proprietary grinding and etching steps are typically performed. However, what is additionally needed is a way to reduce overall cycle times at the incoming and outgoing wafer inspection steps.